Planar transistors are often used to fabricate integrated circuits. A planar transistor has a diffused source electrode and a diffused drain electrode separated by a channel region. Overlying the channel region is a gate electrode that is separated from the channel region by a gate oxide. Planar transistors, although used and useful in many integrated circuit applications, are substrate area intensive. In other words, planar transistors consume a large amount of substrate surface area per transistor. In addition, with integrated circuit geometries decreasing into sub-micron ranges, planar transistors have various disadvantages. At smaller geometries and thinner gate oxide thicknesses, well documented problems such as hot carrier injection, leakage currents, isolation, short channel behavior, and channel length variations are major problems in planar transistors.
To overcome some of the disadvantages described above for planar transistors, elevated source and drain transistors, lightly doped drain (LDD) transistors, and other improvements were developed. Although the improvements reduced some of the disadvantages listed above, the improvements had some undesirable characteristics. The primary undesirable characteristic is the fact that the improved transistors were, in most cases, as area intensive or more area intensive than the planar transistor.
Various approaches have been used to try to reduce transistor surface area and increase transistor packing density while at the same time reducing some of the adverse effects described above. The surrounding gate transistor (SGT) was developed wherein a spacer gate and planar diffusions are used to form a transistor having a vertical current flow (i.e. a vertically directed channel region). The SGT reduced some of the disadvantages that affect planar transistors and reduced surface area due to a vertically positioned spacer gate.
Topography problems and the geometry of the SGT usually result in source contacts, drain contacts, and gate contacts which are difficult to achieve and are difficult to consistently produce using sub-micron technology. The contact to the spacer gate is very difficult to manufacture due to the fact that the spacer gate is contacted from the top. Spacers have a small top-down surface area and are difficult to contact from the top. In addition, the source and drain must not be electrically short circuited when contacting the spacer gate. Therefore, the gate contact for the SGT is extremely alignment and etch critical. In addition, doping of source regions, drain regions, and channel regions via implants can be difficult due to transistor geometry and may require special processing.
Other vertical transistors are known in the art. These transistors typically require trench processing or polysilicon-grown gate dielectrics. Both trench processing and polysilicon-grown gate dielectrics are undesirable in most cases, primarily due to reliability constraints.
In order to further increase circuit density and manufacturing reliability, vertical transistors structures and processes must improve.